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Chapter 1: About This MegaCore Function
Features
1–3
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Input/Output Avalon ? Memory-Mapped (Avalon-MM) master and slave
Logical layer modules with burst support
Avalon streaming (Avalon-ST) interface for custom implementation of message
passing
Doorbell module supporting 16 outstanding DOORBELL packets with time-out
mechanism
Support for preservation of transaction order between outgoing DOORBELL
messages and I/O write requests
New registers and interrupt indicate NWRITE_R transaction completion
Support for preservation of transaction order between outgoing I/O read
requests and I/O write requests from Avalon-MM interfaces
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Qsys support
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
Support for OpenCore Plus evaluation
Supported Transactions
The RapidIO IP core supports the following RapidIO transactions:
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NREAD request and response
NWRITE request
NWRITE_R request and response
SWRITE request
MAINTENANCE read request and response
MAINTENANCE write request and response
MAINTENANCE port-write request
DOORBELL request and response
May 2013
Altera Corporation
RapidIO MegaCore Function
User Guide
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